1. Field of the Invention
This invention relates to semiconductor packages, and more particularly, to a Ball Grid Array (BGA) semiconductor package having a semiconductor chip with center bond pads.
2. Description of Related Art
A conventional semiconductor package is illustrated in FIG. 11, as designated by the reference numeral 1. As shown, this semiconductor package 1 includes a lead frame 11 on which a semiconductor chip 12 is mounted by means of a double-sided adhesive tape 110 which is adhered on the leads 111 of the lead frame 11. The chip 12 is electrically connected to the inner leads 111a of the leads 111 via gold wires 13. Further, an encapsulant 14 is formed through a molding process to hermetically enclose the chip 12, the gold wires 13, and the inner leads 111a of the leads 111 therein. In use, the semiconductor package 1 is mounted on a circuit board.
The outer leads 111b of the leads 111 are first horizontally outwardly extended and then downwardly bent. The ends of the outer leads 111b thus are spaced at intervals greater than the distance between the opposite sides of the encapsulant 14. As a result, the printed circuit board (PCB) area taken up by the semiconductor package 1 includes an apron area, which extend around the perimeter of the semiconductor package 1. When several semiconductor packages of this type are mounted onto a printed circuit board, the collective apron areas thereof take up a significant amount of PCB space, and prevent a close spacing between the packages. Therefore, the size of a printed circuit board is unable to be minimized.
A solution to the foregoing problem is the so-called Ball Grid Array (BGA) technology. A conventional BGA semiconductor package 2 is illustrated in FIG. 12. As shown, the BGA semiconductor package 2 comprises a substrate 21 having first conductive traces 212 formed on an upper surface 211 thereof. The fist conductive traces 212 are electrically connected to second conductive traces 215 formed on a lower surface 214 of the substrate 21 through vias or plated through-holes 213. The second conductive traces 215 each terminate with a contact pad 216 where a conductive solder ball 25 is attached. The chip 22 can thus be electrically connected to a printed circuit board via the solder balls 25, which are arranged in an array pattern. A chip 22 is attached to the upper surface 211 of the substrate 21 on which a plurality of bonding pads 23 are formed. Each of the bonding pad 23 is electrically connected to the fist conductive traces 212 by means of gold wires 24. The chip 22, gold wires 24 and the first conductive traces 212 are then covered by an encapsulant 26.
In the forgoing BGA semiconductor package 2 shown in FIG. 12, the use of the solder balls 25 for I/O connections would save more layout space on the circuit board than the semiconductor package 1 shown in FIG. 11. This is because the solder balls 25 are provided on the lower surface 214 of the substrate 21 without having an apron area resulting from the outwardly extending outer leads 111b as in the case of the semiconductor package 1 shown in FIG. 11. This arrangement allows the area occupied by the BGA semiconductor package 2 on the circuit board to be substantial equal to the package size, thus saving more layout space on the circuit board. The circuit board can thus be made more compact in size.
One drawback to the foregoing BGA semiconductor package 2 shown in FIG. 12, however, is that the gold wires 24 bonded radially from the periphery of the chip 22 to the first conductive traces 212 would cause the projection area of the encapsulant 26 to be considerably larger than that of the chip 22, thus making the size of the resulted package still unsatisfactorily large in size. Moreover, the BGA semiconductor package 2 is quite costly to manufacture since the substrate 21 is quite expensive. The use of the BGA semiconductor package 2 is therefore still unsatisfactory.
A solution to downsize the BGA semiconductor package is the so-called Chip Scale Package (CSP) technique. A conventional CSP semiconductor package 3 is illustrated in FIG. 13. As shown, this CSP semiconductor package 3 is characterized by the fact that the projection area of the substrate 31 is only slightly larger than that of the chip 32, which allows the resulted package to be very compact in size.
One drawback to the foregoing CSP semiconductor package 3, however, is that it requires the use of a BGA substrate as well as advanced flip-chip and solder bumping techniques to assemble and is therefore very costly to manufacture. For this reason, it is only suitable for high-end IC products and unsuited for low-end ones.
A cost-effective solution to the foregoing problem is disclosed in U.S. Pat. No. 5,663,594. The semiconductor package of this patent is schematically illustrated in FIG. 14, as designated by the reference numeral 4. As shown, this semiconductor package 4 includes a chip 42 mounted on the inner ends of the leads 412 of the lead frame 41. A plurality of gold wires 43 are used to electrically connect the chip 42 to the leads 412. An encapsulant 44 is formed to hermetically enclose the chip 42, the gold wires 43, and the loads 412 therein. Further, the encapsulant 44 is formed with a plurality of holes connected to the lower surface of the leads 412. Solder balls 45 can then be adhered to the lower surface of the leads 412 through the holes of the encapsulant 44, such that the resultant package can be electrically connected to a circuit board.
The foregoing semiconductor package 4 is very compact in size and can be manufactured by using existing packaging equipment and process. One drawback to it, however, is that it is only suitable for package chips of the type having peripheral bond pads but unsuitable for pack chips of the type having center bond pads. To appropriately cover leads 412 in the encapsulant 44, the thickness from the lower surface of the leads 412 to the bottom side of the encapsulant 44 should be spacious enough; otherwise, the encapsulant 44 would easily crack when curing. This requirement, however, would make the resultant package 4 disadvantageous in thickness. Moreover, since the holes that are formed in the encapsulant 44 and connected to the lower surface of the leads 412, are very small in diameter, the encapsulating resin used to form the encapsulant 44 would flash to the bottom of these holes, causing the subsequently arranged solder balls 45 to be leasely soldered to the lower surface of the leads 412. The yield rate of the resultant product is thus low. One solution to this problem is to perform a hole-cleaning process right after the holes are completely formed. This solution, however, would make the overall packaging process more complex and costly to implement.
It is therefore an objective of the present invention to provide a BGA semiconductor package with exposed base layer, which is simple in structure and cost-effective to manufacture.
It is another objective of the present invention to provide a BGA semiconductor package with exposed base layer, which is compact in size.
It is still another objective of the present invention to provide a BGA semiconductor package with exposed base layer, which can be manufactured by using known packaging equipment and process.
It is yet another objective of the present invention to provide a BGA semiconductor package with exposed base layer, which is suitable for packaging semiconductor chips of the type having center bond pads.
It is still yet another objective of the present invention to provide a BGA semiconductor package with exposed base layer, which uses a lead frame instead of a BGA substrate for a semiconductor chip to attach thereto.
In accordance with the foregoing and other objectives of the present invention, a BGA semiconductor package with exposed base layer is provided. The BGA semiconductor package of the invention includes the following constituent parts: (a) a base layer having an opening portion in the center thereof and formed with a plurality of holes about the opening portion, wherein the base layer has a first surface and a second opposed surface; (b) a lead frame having a plurality of leads, wherein each of the leads has a lower surface and an upper surface attached to the second surface of the base layer in a manner that inner end portions of the leads extend to the opening portion of the base layer and the upper surface of each of the leads is connected to the corresponding hole of the base layer, (c) a chip attached to the lower surface of the leads; (d) a plurality of bonding wires for electrically interconnecting the chip and the inner end portion of the leads; (e) an encapsulant encapsulating the chip, the bonding wires, and the leads, wherein the first surface of the base layer is exposed to the encapsulant, and (f) a plurally of solder balls electrically connected to the upper surface of the leads through the holes.
In another preferred embodiment, the BGA semiconductor package of the invention can be constructed in such a manner that the encapsulant is formed to encapsulate the semiconductor chip, the bonding wires and the leads, while leaving the first surface of the base layer and a bottom side of the semiconductor chip exposed to the encapsulant
In still another preferred embodiment, the BGA semiconductor package of the invention can be constructed in such a manner that the encapsulant is formed encapsulate to the semiconductor chip, the bonding wires, and the leads, while leaving the first surface of the base layer and the lower surface of outer end portions of the leads exposed to tie encapsulant. This embodiment allows two or more units of the BGA semiconductor package of the invention to be stacked together for higher integration on the circuit board, by making the solder balls of a BGA semiconductor package in an upper position come into contact with the exposed portion of the lower surface of the leads of another BGA semiconductor package in a lower position.
Moreover, the base layer can be a non-conductive tape made of polyimide resin or a solder mask made of epoxy resin. In the case where a solder mask is used as the base layer, the solder mask is applied to the leads of the lead frame by means of coating.